using System;

namespace RapidHDL
{
    /// <summary>
    /// Summary description for AndGate.
    /// </summary>
    public class ROM : TruthTableComponent
    {
        public NodeVector I_Address;
        public NodeVector O_Value;

        int iDepth;
        int iWidth;
        int iAddressWidth;

        public ROM(Component poParentComponent, string psName, int piWidth, int piDepth)
            : base(poParentComponent, psName)
        {
            iWidth = piWidth;
            iDepth = piDepth;
            iAddressWidth = Conversion.MinBitWidth(piDepth-1);
            this.GetTruthTable("ROM_" + psName, iAddressWidth, piWidth);
            I_Address = this.CreateNodeVector("ADDRESS_I", iAddressWidth, NodeFlowType.Sink);
            O_Value = this.CreateNodeVector("VALUE_O", iWidth, NodeFlowType.Source);
        }

        protected override void GenerateTruthTable()
        {
            string sInput;

            this.TruthTable.AddTableEntry("default", Conversion.IntToBinaryString(0,iWidth));
        }

        public void AddEntry(int piAddress, int piValue)
        {
            this.TruthTable.AddTableEntry(Conversion.IntToBinaryString(piAddress, iAddressWidth ), Conversion.IntToBinaryString(piValue, iWidth));
        }

        public void AddTable(System.Collections.Generic.Dictionary<int,int> pdicTable)
        {
            foreach (int iAddress in pdicTable.Keys)
            {
                AddEntry(iAddress, pdicTable[iAddress]);
            }
        }

        public override bool TransformStructureToVerilog()
        {
            WriteVerilogLookupTable();
            return true;
        }
    }
}

